1. Technical Field
The present application relates generally to the field of circuit design and testing. More specifically, the present application is directed to an apparatus and method for extracting a maximum pulse width of a pulse width limiter.
2. Description of Related Art
In many modern computer applications, especially those dealing with large arrays, the maximum pulse width of clock signals operating on these arrays needs to be limited. If the pulse width is too wide, for example, it can cause pre-charged array nodes to lose their logic value and result in array failure. Thus, it is common for a clock source to be pulse-width limited before being asserted onto array grids. One example of a technique for limiting the maximum pulse width of a clock source is described in commonly assigned and co-pending U.S. Patent Application Publication No. 2005/0091620 entitled “A Simplified Method for Limiting Clock Pulse Width,” filed on Oct. 23, 2003.
One important issue that needs to be addressed is the off-chip characterization of such a pulse width limiter circuit under typical bandwidth-limited laboratory conditions. For example, a pulse-width limiter with a maximum allowable pulse width of 100 picoseconds (ps) will have significant power at around 1/100 ps (10 GHz). However, typical laboratory equipment that can guarantee signal integrity at such frequencies is often cost-prohibitive.
One possible solution for avoiding such cost-prohibitive laboratory equipment arrangements is to use on-chip characterization of the pulse-width limiter output. This can be accomplished, for example, by sampling the pulse-width limiter output with various phases of a voltage-controlled oscillator (VCO) input. However, this approach relies on the discrete phases available from the VCO and, therefore, the discreteness limits the resolution of this technique. Moreover, unless the VCO is locked by, for example, a phase-locked loop (PLL), the VCO input can be compromise by large jitter at each of its phases, thereby increasing the measurement uncertainty.
An alternative approach is to employ pulse stretcher circuitry. Pulse stretchers are used to extend or stretch the output of, for example, a pulse-width limiter to thereby reduce the bandwidth requirement of the laboratory measurement equipment. This approach, however, is also subject to limitations. In particular, the precise magnitude of the pulse extension caused by the pulse stretchers must be known, which thereby requires characterization of the pulse stretchers' performance itself. Thus, while one can employ the pulse stretchers to bring the test output within the bandwidth requirement of the off-chip laboratory measurement equipment, the desired measurement remains unknown without an often complicated additional characterization of the pulse stretchers themselves.
As a further alternative, in commonly assigned and co-pending U.S. patent application Ser. No. 11/109,090 entitled “System and Method for On/Off-Chip Characterization of Pulse-Width Limiter Outputs,” filed Apr. 19, 2005, describes a circuit capable of extracting the maximum pulse width of a pulse width limiter. With the circuit described in the '090 application, the outputs of cascaded pulse width limiters are delayed by a fixed amount and then combined through an OR gate. The output of the OR gate is then a wide pulse that may be characterized by limited bandwidth laboratory measurement equipment.
As mentioned above, in the exemplary circuit arrangements set forth in the '090 application, the outputs of the pulse width limiters are delayed by a fixed amount prior to being combined at the OR gate. The delay cells required for providing this fixed amount of delay consume a large chip area and may also consume a large amount of power.